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18.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figures 18.25 to 18.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.25 IRIC Setting Timing and SCL Control (1)
2
C bus format, no wait)
8
9
8
A
Clear IRIC
8
9
8
A
Clear IRIC
Section 18 I
1
2
1
2
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00 Mar. 12, 2008 Page 643 of 1178
2
C Bus Interface (IIC)
3
3
1
1
Clear IRIC
REJ09B0403-0100
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