Ss Control Register 2 (Sscr2) - Renesas H8S Family Hardware Manual

17.3.6

SS Control Register 2 (SSCR2)

SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit Bit Name
7 SDOS
6 SSCKOS
5 SCSOS
4 TENDSTS 0
Initial
Value
R/W
0 R/W
0 R/W
0 R/W
R/W
Section 17 Synchronous Serial Communication Unit (SSU)
Description
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
CMOS or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, 14.4.3, Relationship between Data Input/Output
Pins and Shift Register.
0: CMOS output
1: NMOS open drain output
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a CMOS or
an NMOS open drain output.
0: CMOS output
1: NMOS open drain output
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a CMOS or an
NMOS open drain output.
0: CMOS output
1: NMOS open drain output
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
Rev. 1.00 Mar. 12, 2008 Page 561 of 1178
REJ09B0403-0100