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Section 19 LPC Interface (LPC)
19.4.5
Gate A20
The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture
CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware.
The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
(1)
Regular Gate A20 Operation
Output of the Gate A20 signal can be controlled by an H'D1 command and data. When the slave
(this LSI) receives data, it normally reads IDR1 in the interrupt handling routine activated by the
IBFI1 interrupt. At this time, firmware copies bit 1 of data following an H'D1 command and
outputs it on pin GA20.
(2)
Fast Gate A20 Operation
The internal state of pin GA20 is initialized to 1 since the initial value of the FGA20E bit is 0.
When the FGA20E bit is set to 1, pin P81/GA20 functions as the output of the fast GA20 signal.
The state of pin GA20 can be monitored by reading bit GA20 in HICR2.
The initial output from this pin is 1, which is the initial value. Afterward, the host can manipulate
the output from this pin by sending commands and data. This function is only available via the
IDR1. The LPC decodes commands input from the host. When an H'D1 host command is
detected, bit 1 of the data following the host command is output from pin GA20. This operation
does not depend on firmware or interrupts, and is faster than the regular processing using
interrupts. Table 19.6 shows the conditions that set and clear pin GA20. Figure 19.8 shows the
GA20 output flow. Table 19.7 indicates the GA20 output signal values.
Table 19.6 GA20 Setting/Clearing Timing
Pin Name
Setting Condition
GA20
When bit 1 of the data that follows an
H'D1 host command is 1
Rev. 1.00 Mar. 12, 2008 Page 740 of 1178
REJ09B0403-0100
Clearing Condition
When bit 1 of the data that follows an
H'D1 host command is 0
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