A/D Control/Status Register (Adcsr) - Renesas H8S Family Hardware Manual

Table 23.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
23.3.2

A/D Control/Status Register (ADCSR)

The ADCSR controls the operation of the A/D conversion.
Bit Bit Name
7 ADF
6 ADIE
Initial
Value
R/W Description
0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
This flag indicates that the results of A/D conversion are
stored in the A/D data registers.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1
A/D Data Register to Store A/D Conversion
Results
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
When A/D conversion ends in single mode
When A/D conversion ends on all channels specified
in scan mode
When 0 is written after reading ADF = 1
When DTC starts by an ADI interrupt and ADDR is
read
Rev. 1.00 Mar. 12, 2008 Page 899 of 1178
Section 23 A/D Converter
REJ09B0403-0100