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Table 18.9 Examples of Operation Using the DTC
Master Transmit
Mode
Item
Slave address +
Transmission by
R/W bit
DTC (ICDR write)
transmission/
reception
Dummy data
read
Actual data
Transmission by
transmission/
DTC (ICDR write)
reception
Dummy data
(H'FF) write
Last frame
Not necessary
processing
Transfer request
1st time: Clearing
processing after
by CPU
last frame
2nd time: Stop
processing
condition issuance
by CPU
Setting of
Transmission:
number of DTC
Actual data count
transfer data
+ 1 (+1 equivalent
frames
to slave address +
R/W bits)
Master Receive
Slave Transmit
Mode
Mode
Transmission by
Reception by
CPU (ICDR write)
CPU (ICDR read)
Processing by
CPU (ICDR read)
Reception by
Transmission by
DTC (ICDR read)
DTC (ICDR write)
Processing by
DTC (ICDR write)
Reception by
Not necessary
CPU (ICDR read)
Not necessary
Automatic clearing
on detection of
stop condition
during
transmission of
dummy data (H'FF)
Reception: Actual
Transmission:
data count
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
2
Section 18 I
C Bus Interface (IIC)
Slave Receive
Mode
Reception by CPU
(ICDR read)
Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
Rev. 1.00 Mar. 12, 2008 Page 647 of 1178
REJ09B0403-0100
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