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Section 8 I/O Ports
Bit
Bit Name
3
P43DDR
2
P42DDR
1
P41DDR
0
P40DDR
(2)
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins. P4DR is initialized only by a system reset, and retains
the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
7
P47DR
6
P46DR
5
P45DR
4
P44DR
3
P43DR
2
P42DR
1
P41DR
0
P40DR
Rev. 1.00 Mar. 12, 2008 Page 290 of 1178
REJ09B0403-0100
Initial Value
R/W Description
0
W
0
W
0
W
0
W
Initial Value
R/W Description
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
•
Normal extended mode (16-bit bus)
These bits have no effect on operation.
•
Other modes
If port 4 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P4DDR bits are set to 1, and as input port
when cleared to 0.
These bits store output data for the port 4 pins that are
used as the general output port.
If this register is read, the P4DR values are read for the
bits with the corresponding P4DDR bits set to 1. For the
bits with the corresponding P4DDR bits cleared to 0,
the pin states are read.
•
Normal extended mode (16-bit data bus)
Since the corresponding pins function as
bidirectional data bus pins, the value in these bits
has no effect on operation.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, 1 is read.
•
Other modes
These bits store output data for the port 4 pins that
are used as the general output port.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, the pin states are read.
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