Interrupt Requests - Renesas H8S Family Hardware Manual

Interrupt Requests

The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,

transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive

data register full, a transmit data register empty, and a transmit end interrupts can activate the

DTC for data transfer.

Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector

address, and both a transmit data register empty and a transmit end interrupts are allocated to the

SSTXI vector address, the interrupt source should be decided by their flags. Table 17.5 lists the

interrupt sources.

When an interrupt condition shown in table 17.5 is satisfied, an interrupt is requested. Clear the

interrupt source by CPU or DTC data transfer.

Table 17.5 Interrupt Sources

Abbreviation Interrupt Source

Overrun error

Conflict error

Receive data register full

Transmit data register empty

Transmit end

Setting of Module Stop Mode

The SSU can be enabled/disabled by the module stop control register setting and is disabled by the

initial value. Canceling module stop mode enables to access the SSU registers. For details, see

section 28, Power-Down Modes.

Section 17 Synchronous Serial Communication Unit (SSU)

Interrupt Condition

(RIE = 1) • (ORER = 1)

(CEIE = 1) • (CE = 1)

(RIE = 1) • (RDRF = 1)

(TIE = 1) • (TDRE = 1)

(TEIE = 1) • (TEND = 1)

Rev. 1.00 Mar. 12, 2008 Page 583 of 1178

REJ09B0403-0100