Assigning Interrupt Sources To Ep0 - Renesas H8S Family Hardware Manual

22.10.4 Assigning Interrupt Sources to EP0

The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must

be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.

22.10.5 Clearing the FIFO When DTC Transfer is Enabled

The endpoint 1 data register (EPDR1) cannot be cleared when DTC transfer for endpoint 1 is

enabled (EP1DMAE in DMA = 1). Cancel DTC transfer before clearing the register.

22.10.6 Notes on TR Interrupt

Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,

EP2, or EP3.

The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent

from the USB host. However, at the timing shown in figure 22.24, multiple TR interrupts occur

successively. Take appropriate measures against malfunction in such a case.

Note: This module determines whether to return NAK if the FIFO of the target EP has no data

when receiving the IN token, but the TR interrupt flag is set after a NAK handshake is

sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is

Determines whether

to return NAK

TR interrupt routine

Sets TR flag

Figure 22.23 TR Interrupt Flag Set Timing

Section 22 USB Function Module (USB)

transmit data

Determines whether

to return NAK

Sets TR flag

(Sets the flag again)

Rev. 1.00 Mar. 12, 2008 Page 893 of 1178

TR interrupt routine

Transmits data

REJ09B0403-0100