Etherc/E-Dmac Status Interrupt Permission Register (Eesipr) - Renesas H8S Family Hardware Manual

21.2.7

EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)

EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit. In the initial state, interrupts are not enabled.
Bit Bit Name

31
30 TWBIP

29 to 27
26 TABTIP
25 RABTIP
24 RFCOFIP
23 ADEIP
22 ECIIP
21 TCIP
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
value R/W Description
0 R Reserved
This bit is always read as 0. The initial value should not
be changed.
0 R/W Write-Back Complete Interrupt Permission
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
0 R/W Transmit Abort Detection Interrupt Permission
0: Transmit abort detection interrupt is disabled
1: Transmit abort detection interrupt is enabled
0 R/W Receive Abort Detection Interrupt Permission
0: Receive abort detection interrupt is disabled
1: Receive abort detection interrupt is enabled
0 R/W Receive Frame Counter Overflow Interrupt Permission
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
0 R/W Address Error Interrupt Permission
0: Address error interrupt is disabled
1: Address error interrupt is enabled
0 R/W EtherC Status Register Interrupt Permission
0: EtherC status interrupt is disabled
1: EtherC status interrupt is enabled
0 R/W Frame Transmit Complete Interrupt Permission
0: Frame transmit complete interrupt is disabled
1: Frame transmit complete interrupt is enabled
Rev. 1.00 Mar. 12, 2008 Page 803 of 1178
REJ09B0403-0100