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Section 20 Ethernet Controller (EtherC)
20.4.4
Accessing MII Registers
MII registers in the PHY are accessed via this LSI's PHY interface register (PIR). Connection is
made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
(1)
MII Management Frame Format
The format of an MII management frame is shown in figure 20.7. To access an MII register, a
management frame is implemented by the program in accordance with the procedures shown in
(2) MII Register Access Procedure.
Access Type
Item
PRE
Number of bits
Read
Write
[Legend]
PRE:
32 consecutive 1s
ST:
Write of 01 indicating start of frame
OP:
Write of code indicating access type
PHYAD:
Write of 0001 if the PHY address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY address.
REGAD:
Write of 0001 if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY register address.
TA:
Time for switching data transmission source on MII interface
(a) Read: Bus is released (indicated as Z0).
(b) Write: B'10 is written.
DATA:
16-bit data. Sequential write or read from MSB
(a) Read: 16-bit data read
(b) Write: 16-bit data write
IDLE:
Wait time until next MII management format input
(a) Read: Since the bus has been relased at TA already, control is not required.
(b) Write: Independent bus release (indicated as X) is performed.
Rev. 1.00 Mar. 12, 2008 Page 782 of 1178
REJ09B0403-0100
ST
OP
32
2
2
1..1
01
10
1..1
01
01
Figure 20.7 MII Management Frame Format
MII Management Frame
PHYAD
REGAD
5
5
00001
RRRRR
00001
RRRRR
TA
DATA
IDLE
2
16
-
Z0
D..D
-
10
D..D
X
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