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5.4
Interrupt Sources.................................................................................................................. 86
5.4.1
External Interrupts .................................................................................................. 86
5.4.2
Internal Interrupts ................................................................................................... 87
5.5
Interrupt Exception Handling Vector Table......................................................................... 88
5.6
Interrupt Control Modes And Interrupt Operation ................................................................ 91
5.6.1
Interrupt Control Mode 0 ........................................................................................ 93
5.6.2
Interrupt Control Mode 1 ........................................................................................ 95
5.6.3
Interrupt Exception Handling Sequence ................................................................. 98
5.6.4
Interrupt Response Times ....................................................................................... 99
5.6.5
Dtc Activation By Interrupt................................................................................. 100
5.7
Usage Notes ....................................................................................................................... 102
5.7.1
Conflict between Interrupt Generation and Disabling .......................................... 102
5.7.2
Instructions That Disable Interrupts ....................................................................... 103
5.7.3
Interrupts during Execution of EEPMOV Instruction........................................... 103
5.7.4
Irq Status Registers (Isr16, Isr) ....................................................................... 103
Section 6 Bus Controller (BSC).........................................................................105
6.1
Features.............................................................................................................................. 105
6.2
Input/Output Pins ............................................................................................................... 108
6.3
Register Descriptions ......................................................................................................... 109
6.3.1
Bus Control Register (BCR) ................................................................................. 109
6.3.2
Bus Control Register 2 (Bcr2) ............................................................................ 111
6.3.3
Wait State Control Register (Wscr) ................................................................... 112
6.3.4
Wait State Control Register 2 (Wscr2) .............................................................. 114
6.3.5
System Control Register 2 (Syscr2) .................................................................. 115
6.4
Bus Control ........................................................................................................................ 116
6.4.1
Bus Specifications................................................................................................. 116
6.4.2
Advanced Mode.................................................................................................... 123
6.4.3
I/O Select Signals.................................................................................................. 124
6.5
Bus Interface ...................................................................................................................... 125
6.5.1
Data Size and Data Alignment.............................................................................. 125
6.5.2
Valid Strobes ........................................................................................................ 127
6.5.3
Valid Strobes (In Glueless Extension) .................................................................. 128
6.5.4
Basic Operation Timing In Normal Extended Mode ............................................ 129
6.5.5
Basic Operation Timing In Address-Data Multiplex Extended Mode .................. 140
6.5.6
Wait Control ......................................................................................................... 148
6.6
Burst Rom Interface.......................................................................................................... 152
6.6.1
Basic Operation Timing........................................................................................ 152
6.6.2
Wait Control ......................................................................................................... 153
6.7
Idle Cycle........................................................................................................................... 154
Rev. 1.00 Mar. 12, 2008 Page xi of xIviii
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