Instructions That Disable Interrupts - Renesas H8S Family Hardware Manual

Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions are executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit or UI bit is set by one of these instructions, the new value

becomes valid two states after execution of the instruction ends.

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction. Therefore, if an interrupt is generated during execution

of an EEPMOV.W instruction, the following coding should be used.

IRQ Status Registers (ISR16, ISR)

Since IRQnF may be set to 1 according to the pin status after a reset, the ISR16 and the ISR

should be read after a reset, and then write 0 in IRQnF (n = 15 to 0).

Section 5 Interrupt Controller

Rev. 1.00 Mar. 12, 2008 Page 103 of 1178

REJ09B0403-0100