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13.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, see section
13.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card
interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
7
TIE
6
RIE
5
TE
4
RE
3
MPIE
2
TEIE
Initial
Value
R/W
Description
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, see section 13.5, Multiprocessor
Communication Function.
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Section 13 Serial Communication Interface (SCI)
Rev. 1.00 Mar. 12, 2008 Page 437 of 1178
REJ09B0403-0100
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