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Transmit descriptor
31 30 29 28 27 26
T
T
T
T
T
F
A
D
F
F
TD0
E
C
L
P
P
T
E
1
0
31
TD1
TDL
31
TD2
Figure 21.2 Relationship between Transmit Descriptor and Transmit Buffer
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
TFS26 to TFS0
16
15
Fixed at H'0000
TBA
Padding (4 bytes)
Transmit buffer
0
Valid transmit data
0
0
Rev. 1.00 Mar. 12, 2008 Page 817 of 1178
REJ09B0403-0100
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