Renesas H8S Family Hardware Manual page 877

Reception flowchart
This LSI + memory
EtherC/E-DMAC
initialization
Descriptor and
receive
buffer setting
Start of reception
Descriptor read
Receive data transfer
Descriptor write-back
Descriptor read
Receive data transfer
Descriptor write-back
Descriptor read (receive
ready for the next frame)
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
E-DMAC Receive FIFO
Reception
completed
Figure 21.5 Sample Reception Flowchart
EtherC
Frame reception
Rev. 1.00 Mar. 12, 2008 Page 829 of 1178
Ethernet
REJ09B0403-0100