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Operation Timing - Renesas H8S Family Hardware Manual

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Section 11 8-Bit Timer (TMR)

11.3

Operation Timing

11.3.1
TCNT Count Timing
Figure 11.3 shows the TCNT count timing with an internal clock source.
φ
External clock
input pin
TCNT input
clock
TCNT
11.3.2
Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 11.4
shows the timing of CMF flag setting.
φ
TCNT
TCOR
Compare-match
signal
CMF
Figure 11.4 Timing of CMF Setting at Compare-Match
Rev. 1.00 Mar. 12, 2008 Page 404 of 1178
REJ09B0403-0100
N – 1
Figure 11.3 Count Timing for Internal Clock Input
N
N
N
N + 1
N + 1

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