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Section 6 Bus Controller (BSC)
(3)
16-Bit, 2-State Data Access Space
Figures 6.19 to 6.24 show bus timings for a 16-bit, 2-state access space. When a 16-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and
the lower half (AD7 to AD0) for odd addresses. Wait states cannot be inserted.
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)
Rev. 1.00 Mar. 12, 2008 Page 142 of 1178
REJ09B0403-0100
Read Cycle
Address
T
T
T
1
AW
φ
Address
Address
Data
Address
T
T
T
T
2
3
4
1
AW
Data
Address
Address
Write Cycle
Data
T
T
T
2
3
4
Data
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