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Event Counter Handling Priority - Renesas H8S Family Hardware Manual

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Section 7 Data Transfer Controller (DTC)
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the
same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced
with address code that is generated by the ECS flag status.
When the DTC transfer is completed, the ECS flag for transfer is cleared.
Table 7.3
Flag Status/Address Code
15
14
13
12
1
1
0
1
0
0
1
0
0
0
7.3.1

Event Counter Handling Priority

EVENT0 to EVENT15 count handling is operated in the priority shown as below.
High
EVENT0 > EVENT1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ EVENT14 > EVENT15
Rev. 1.00 Mar. 12, 2008 Page 170 of 1178
REJ09B0403-0100
ECS
11
10
9
8
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Low
3
2
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address
Code
B'00000
B'00010
B'00100
B'00110
B'01000
B'01010
B'01100
B'01110
B'10000
B'10010
B'10100
B'10110
B'11000
B'11010
B'11100
B'11110

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