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Section 7 Data Transfer Controller (DTC)
Interrupt controller
Interrupt
request
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF:
DTVECR:
Rev. 1.00 Mar. 12, 2008 Page 160 of 1178
REJ09B0403-0100
DTC
DTC mode register A, B
DTC transfer count register A, B
DTC source address register
DTC destination address register
DTC enable registers A to F
DTC vector register
Figure 7.1 Block Diagram of DTC
Internal address bus
Internal data bus
On-chip RAM
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