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Section 9 14-Bit PWM Timer (PWMX)
9.2
Input/Output Pins
Table 9.1 lists the PWMX (D/A) module input and output pins.
Table 9.1
Pin Configuration
Name
PWMX output pin 0
PWMX output pin 1
PWMX output pin 2
PWMX output pin 3
9.3
Register Descriptions
The PWMX (D/A) module has the following registers. For details on the module stop control
register, see section 28.1.3, Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL,
MSTPCRA).
• PWMX (D/A) counter (DACNT)
• PWMX (D/A) data register A (DADRA)
• PWMX (D/A) data register B (DADRB)
• PWMX (D/A) control register (DACR)
• Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.
Rev. 1.00 Mar. 12, 2008 Page 358 of 1178
REJ09B0403-0100
Abbreviation I/O
PWX0
Output
PWX1
Output
PWX2
Output
PWX3
Output
Function
PWM timer pulse output of PWMX_0 channel A
PWM timer pulse output of PWMX_0 channel B
PWM timer pulse output of PWMX_1 channel A
PWM timer pulse output of PWMX_1 channel B
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