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Section 8 I/O Ports
PBn input
1 expected
PBnDR
0 expected
PBnDR
(n = 3 to 0)
(7)
Pin Functions
• PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK
PB4/EVENT12/RM_TX-EN
The pin function is switched as shown below according to the PBnDDR bit. When using this
pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O
pins when the EtherC is enabled.
EtherC,
E-DMAC
PBnDDR
Event
Disabled
counter
Pin
PBn input pin
function
[Legend]
n = 7 to 4, m = 15 to 8, X: Don't care.
Note:
* See section 7.3, DTC Event Counter, for the event counter settings.
Rev. 1.00 Mar. 12, 2008 Page 334 of 1178
REJ09B0403-0100
Figure 8.12 Noise Canceler Operation
Either of them is stopped
0
Enabled
EVENTm input
pin
1
X
PBn output pin
Both of them are
stopped
X
X
RM_xxxx
EtherC I/O pin
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