Renesas H8S Family Hardware Manual page 193

φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)
φ
CP256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)
Read Cycle
Address Data
T T T T
1 AW 2 3
Address
Address
Read Cycle
Address Data
T T T T
1 2 3 4
Address Data
Data
Address
Section 6 Bus Controller (BSC)
Write Cycle
Address
T T T T
4 1 AW 2
Data
Address
Data
Address
Write Cycle
Address Data
T T T
1 2 3
Address
Address
Rev. 1.00 Mar. 12, 2008 Page 145 of 1178
Data
T T
3 4
Data
Data
T
4
Data
Data
REJ09B0403-0100