Advertisement
Section 8 I/O Ports
8.2
I/O Ports for the H8S/2462 Group
Table 8.9 is a summary of the port functions. The pins of each port also function as input/output
pins of peripheral modules and interrupt input pins. Each input/output port includes a data
direction register (DDR) that controls input/output and a data register (DR) that stores output data.
DDR and DR are not provided for input-only ports.
Pins of ports 1 to 4, 6, and A and pins D0 to D5 of port D have built-in input pull-up MOSs. For
port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their
respective DDR and the output data register (ODR). Ports 1 to 3, and 6 have an input pull-up MOS
control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up
MOSs.
Port 3 pins and pins 47 to 44 and B3 to B0 have built-in de-bouncers (DBn) that eliminate noises
in the input signals.
Ports 4 and F are designed for retain state outputs (RSn), which retain the output values on the
pins even if a reset is generated when the watchdog timer has overflowed.
Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports
can drive a Darlington transistor in output mode. Port pins 80 to 83, C0 to C5, D6, and D7 are
NMOS push-pull output.
Rev. 1.00 Mar. 12, 2008 Page 270 of 1178
REJ09B0403-0100
Advertisement
