Lpc Interface Serialized Interrupt Operation (Serirq) - Renesas H8S Family Hardware Manual

LPC Interface Serialized Interrupt Operation (SERIRQ)

A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a

host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the

serialized interrupt transfer cycle generated by the host or a peripheral function, and a request

signal is generated by the frame corresponding to that interrupt. The timing is shown in figure

Drive source

H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample

H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle

Host controller

IOCHCK frame

Figure 19.10 SERIRQ Timing

Host controller

Rev. 1.00 Mar. 12, 2008 Page 747 of 1178

Section 19 LPC Interface (LPC)

REJ09B0403-0100