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19.3.14 SERIRQ Control Register 2 (SIRQCR2)
SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host
interrupt request outputs.
Bit
Bit Name Initial Value Slave Host Description
7
IEDIR3
0
6 to 0
All 0
R/W
R/W
Interrupt Enable Direct Mode 3
Selects whether an SERIRQ interrupt generation of
LPC channel 3 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the
enable bit.
0: A host interrupt is generated when both the
enable bit and the corresponding OBF flag are
set
1: A host interrupt is generated when the enable bit
is set
R/W
Reserved
The initial value should not be changed.
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 707 of 1178
REJ09B0403-0100
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