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Section 18 I
C Bus Interface (IIC)
Stop condition
Start condition
(a)
SDA
A
Bit 0
SCL
9
8
Internal clock
BBSY bit
Master receive mode
ICDR read
disabled period
Start condition
Execution of instruction
Confirmation of stop
issuance
for issuing stop condition
condition issuance
(write 0 to BBSY and SCP)
(read BBSY = 0)
Figure 18.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 1.00 Mar. 12, 2008 Page 656 of 1178
REJ09B0403-0100
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