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Section 7 Data Transfer Controller (DTC)
7.6.7
Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number
of states required for each execution status.
Table 7.8
DTC Execution Status
Vector Read
Mode
I
Normal
1
Repeat
1
Block transfer
1
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.9
Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution
Vector read
status
Register
information
read/write
Byte data read S
Word data read
Byte data write S
Word data write
Internal operation
Rev. 1.00 Mar. 12, 2008 Page 182 of 1178
REJ09B0403-0100
Register
Information
Read/Write
J
6
6
6
On-Chip RAM
On-Chip RAM
(On-chip RAM area
(H'FFEC00 to
other than H'FFEC00 to
H'FFEFFF)
H'FFEFFF)
32
16
1
1
S
—
—
I
1
—
S
J
1
1
K
1
1
S
K
1
1
L
1
1
S
L
1
1
S
M
Data Read
Data Write
K
L
1
1
1
1
N
N
On-
On-Chip
Chip
I/O
ROM
Registers
External Devices
16
8
16
8
1
2
2
2
1
—
—
4
—
—
—
—
1
2
2
2
1
4
2
4
1
2
2
2
1
4
2
4
1
1
1
1
Internal
Operations
M
3
3
3
8
16
16
3
2
3
6 + 2m
2
3 + m
—
—
—
3 + m
2
3 + m
6 + 2m
2
3 + m
3 + m
2
3 + m
6 + 2m
2
3 + m
1
1
1
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