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Section 8 I/O Ports
8.2.11
Port B
Port B is an 8-bit I/O port. Port B pins can also function as the event counter input, de-bounced
input, and EtherC control input/output pins. The pin functions change according to the operating
mode. Port B has the following registers.
• Port B data direction register (PBDDR)
• Port B output data register (PBODR)
• Port B input data register (PBPIN)
• Noise canceler enable register (P4BNCE)
• Noise canceler mode control register (P4BNCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit
Bit Name
7
PB7DDR
6
PB6DDR
5
PB5DDR
4
PB4DDR
3
PB3DDR
2
PB2DDR
1
PB1DDR
0
PB0DDR
Rev. 1.00 Mar. 12, 2008 Page 330 of 1178
REJ09B0403-0100
Initial Value
R/W Description
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
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