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(2)
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit
Bit Name
7
P97DR
6
P96DR
5
P95DR
4
P94DR
3
P93DR
2
P92DR
1
P91DR
0
P90DR
(3)
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P97/WAIT/CS256
The pin function is switched as shown below according to the operating mode and the
combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in
WSCR2, and the P97DDR bit.
Operating
mode
WMS1,
WMS21
CS256E
P97DDR
0
Pin function
P97 input pin P97 output
[Legend] X: Don't care.
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Extended mode
All 0
0
1
pin
Description
P9DR stores output data for the port 9 pins that are
used as the general output port.
If this register is read, the P9DR values are read for
the bits with the corresponding P9DDR bits set to 1.
For the bits with the corresponding P9DDR bits
cleared to 0, the pin states are read.
Either bit is 1
1
X
CS256 output
WAIT input
pin
pin
Rev. 1.00 Mar. 12, 2008 Page 319 of 1178
Section 8 I/O Ports
Single-chip mode
X
X
X
X
0
P97 input pin P97 output
REJ09B0403-0100
1
pin
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