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20.2
Input/Output Pins
Table 20.1 lists the pin configuration of the EtherC.
Table 20.1 Pin Configuration
Type
Abbreviation
RMII
RM_REF-CLK
interface
signals
RM_TX-EN
RM_TXD1
RM_TXD0
RM_CRS-DV
RM_RXD1
RM_RXD0
RM_RX-ER
PHY
MDC
register
interface
MDIO
signals
Others
LNKSTA
WOL
I/O
Function
Input
Transmit/Receive Clock
Timing reference signal for the RM_TX-EN, RM_TXD1
to RM_TXD0, RM_CRS-DV, RM_RXD1 to RM_RXD0,
and RM_RX-ER signals
Output
Transmit Enable
Indicates that transmit data is ready on pins RM_TXD1
and RM_TXD0.
Output
Transmit Data
2-bit transmit data
Input
Carrier Detection/Receive Data Valid
Carrier detection signal/Signal that indicates that valid
receive data is on pins RM_RXD1 and RM_RXD0.
Input
Receive Data
2-bit receive data
Input
Receive Error
Indicates the error state during data reception.
Output
Management Data Clock
Reference clock signal for information transfer via MDIO
Input/
Management Data I/O
Output
Bidirectional signal for exchange of management
information between the station management entity
(STA) and physical layer (PHY)
Input
Link Status
Inputs link status from PHY-LSI
Output
Wake-On-LAN
Signal indicating reception of Magic Packet
Section 20 Ethernet Controller (EtherC)
Rev. 1.00 Mar. 12, 2008 Page 759 of 1178
REJ09B0403-0100
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