Renesas H8S Family Hardware Manual page 715

Figure 19.1 shows a block diagram of the LPC.

Cycle detection

Serial → parallel conversion

Serial ← parallel conversion

HICR0 to HICR5:

Host interface control registers 0 to 5

LADR12H, LADR12L:

LPC channel 1, 2 address registers 12H and 12L

LADR3H, LADR3L:

LPC channel 3 address registers 3H and 3L

IDR1 to IDR3:

Input data registers 1 to 3

ODR1 to ODR3:

Output data registers 1 to 3

STR1 to STR3:

Status registers 1 to 3

Module data bus

Parallel → serial conversion

SIRQCR0 to 5

Control logic

Address match

HICR0 to HICR5

Internal interrupt

Figure 19.1 Block Diagram of LPC

TWR1 to TWR15:

SIRQCR0 to SIRQCR5:

Rev. 1.00 Mar. 12, 2008 Page 667 of 1178

Section 19 LPC Interface (LPC)

Bidirectional data register 0MW

Bidirectional data register 0SW

Bidirectional data registers 1 to 15

SERIRQ control registers 0 to 5

Host interface select register

REJ09B0403-0100