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5.6.4
Interrupt Response Times
Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.7 are explained in table 5.8.
Table 5.7
Interrupt Response Times
No.
Execution Status
1
Interrupt priority determination*
2
Number of wait states until executing instruction ends*
3
PC, CCR stack save
4
Vector fetch
5
Instruction fetch*
6
Internal processing*
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.8
Number of States in Interrupt Handling Routine Execution Status
Symbol
Instruction fetch S
I
Branch address read S
Stack manipulation S
[Legend]
m:
Number of wait states in external device access.
1
3
4
Total (using on-chip memory)
Internal
Memory
1
J
K
Section 5 Interrupt Controller
Advanced Mode
3
2
1 to (19 + 2·S
2·S
2·S
2·S
2
12 to 32
Object of Access
External Device
8-Bit Bus
2-State
3-State
Access
Access
4
6 + 2m
Rev. 1.00 Mar. 12, 2008 Page 99 of 1178
)
I
K
I
I
16-Bit Bus
2-State
3-State
Access
Access
2
3 + m
REJ09B0403-0100
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