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18.6 Usage Notes ....................................................................................................................... 651
Section 19 Lpc Interface (Lpc)........................................................................ 665
19.1 Features.............................................................................................................................. 665
19.2 Input/Output Pins............................................................................................................... 668
19.3 Register Descriptions......................................................................................................... 669
19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 671
19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 679
19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 682
19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 683
19.3.5 Pin Function Control Register (PINFNCR) .......................................................... 684
19.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)..................... 684
19.3.7 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................. 686
19.3.8 Input Data Registers 1 to 3 (IDR1 to IDR3) ......................................................... 689
19.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3) ................................................... 689
19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 690
19.3.11 Status Registers 1 to 3 (STR1 to STR3) ............................................................... 691
19.3.12 SERIRQ Control Register 0 (SIRQCR0).............................................................. 699
19.3.13 SERIRQ Control Register 1 (SIRQCR1).............................................................. 703
19.3.14 SERIRQ Control Register 2 (SIRQCR2).............................................................. 707
19.3.15 SERIRQ Control Register 3 (SIRQCR3).............................................................. 708
19.3.16 SERIRQ Control Register 4 (SIRQCR4).............................................................. 709
19.3.17 SERIRQ Control Register 5 (SIRQCR5).............................................................. 710
19.3.18 Host Interface Select Register (HISEL)................................................................ 711
19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 712
19.3.20 SMIC Flag Register (SMICFLG) ......................................................................... 713
19.3.21 SMIC Control Status Register (SMICCSR).......................................................... 714
19.3.22 SMIC Data Register (SMICDTR) ........................................................................ 714
19.3.23 SMIC Interrupt Register 0 (SMICIR0) ................................................................. 715
19.3.24 SMIC Interrupt Register 1 (SMICIR1) ................................................................. 717
19.3.25 BT Status Register 0 (BTSR0).............................................................................. 718
19.3.26 BT Status Register 1 (BTSR1).............................................................................. 721
19.3.27 BT Control Status Register 0 (BTCSR0).............................................................. 724
19.3.28 BT Control Status Register 1 (BTCSR1).............................................................. 725
19.3.29 BT Control Register (BTCR)................................................................................ 727
19.3.30 BT Data Buffer (BTDTR)..................................................................................... 730
19.3.31 BT Interrupt Mask Register (BTIMSR)................................................................ 730
19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0) ........................................................ 732
19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1) ........................................................ 732
19.4 Operation ........................................................................................................................... 733
Rev. 1.00 Mar. 12, 2008 Page xx of xIviii
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