Input/Output Pins - Renesas H8S Family Hardware Manual

17.2

Input/Output Pins

Table 17.1 shows the SSU pin configuration.
Table 17.1 Pin Configuration
Pin Name I/O
SSCK I/O
SSI I/O
SSO I/O
SCS
I/O
17.3 Register Descriptions
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS control register 2 (SSCR2)
• SS transmit data register 0 (SSTDR0)
• SS transmit data register 1 (SSTDR1)
• SS transmit data register 2 (SSTDR2)
• SS transmit data register 3 (SSTDR3)
• SS receive data register 0 (SSRDR0)
• SS receive data register 1 (SSRDR1)
• SS receive data register 2 (SSRDR2)
• SS receive data register 3 (SSRDR3)
• SS shift register (SSTRSR)
Section 17 Synchronous Serial Communication Unit (SSU)
Function
SSU clock input/output
SSU data input/output
SSU data input/output
SSU chip select input/output
Rev. 1.00 Mar. 12, 2008 Page 553 of 1178
REJ09B0403-0100