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Serirq Control Register 3 (Sirqcr3) - Renesas H8S Family Hardware Manual

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Section 19 LPC Interface (LPC)

19.3.15 SERIRQ Control Register 3 (SIRQCR3)

SIRQCR3 selects the SERIRQ interrupt requests of the SCIF.
Bit
Bit Name
7 to 4 
3
SCSIRQ3
2
SCSIRQ2
1
SCSIRQ1
0
SCSIRQ0
Rev. 1.00 Mar. 12, 2008 Page 708 of 1178
REJ09B0403-0100
R/W
Initial
Value
Slave Host Description
All 0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Reserved
The initial value should not be changed.
SCIF SERIRQ Interrupt Select
These bits select the SCIF interrupt request to the
host.
0000: No interrupt request to the host
0001: HIRQ1
0010: SMI
0011: HIRQ3
0100: HIRQ4
0101: HIRQ5
0110: HIRQ6
0111: HIRQ7
1000: HIRQ8
1001: HIRQ9
1010: HIRQ10
1011: HIRQ11
1100: HIRQ12
1101: HIRQ13
1110: HIRQ14
1111: HIRQ15

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