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t
f1
t
H1
t
= t
f1
f2
t
+ t
H1
t
t
H1
t
= t
f1
t
+ t
H1
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.5.
Table 9.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
Duty cycle of base pulse
Figure 9.5 D/A Data Register Configuration when CFS = 1
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 9.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
t
f2
t
H2
= t
= ··· = t
= t
= T× 64
f3
f255
f256
+ t
+ ··· + t
+ t
= T
H2
H3
H255
H256
a. CFS = 0 [base cycle = resolution (T) × 64]
t
f1
f2
t
H2
= t
= ··· = t
= t
= T× 256
f2
f3
f63
f64
+ t
+ ··· + t
+ t
= T
H2
H3
H63
H64
b. CFS = 1 [base cycle = resolution (T) × 256]
DA8
DA7
1 conversion cycle
t
f255
t
t
H3
H255
H
1 conversion cycle
t
t
H3
H63
H
DA6
DA5
DA4
DA3
Location of additional pulses
Rev. 1.00 Mar. 12, 2008 Page 369 of 1178
Section 9 14-Bit PWM Timer (PWMX)
t
f256
t
H256
t
t
f63
f64
t
H64
)
H
DA2
DA1
DA0
REJ09B0403-0100
CFS
1
1
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