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When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3,
ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address
match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of
bits 3 to 0 are ignored.
Register selection according to the bits ignored in address match determination is as shown in the
following table.
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
Bit 4
Bits 15 to5
I/O Address
Bit 3
Bit 2
Bit 1
Bit 3
0
Bit 1
Bit 3
1
Bit 1
Bit 3
0
Bit 1
Bit 3
1
Bit 1
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
1
1
1
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
1
1
1
Section 19 LPC Interface (LPC)
Transfer
Bit 0
Cycle
0
I/O write
0
I/O write
0
I/O read
0
I/O read
0
I/O write
1
I/O write
•
•
•
1
0
I/O read
1
I/O read
•
•
•
1
Rev. 1.00 Mar. 12, 2008 Page 687 of 1178
Host Register
Selection
IDR3 write, C/D3 ← 0
IDR3 write, C/D3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15
write
TWR0SW read
TWR1 to TWR15
read
REJ09B0403-0100
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