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Table Of Contents - Renesas H8S Family Hardware Manual

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22.5.3 Suspend and Resume Operations.......................................................................... 867
22.5.4 Control Transfer.................................................................................................... 872
22.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 878
22.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 879
22.5.7 EP3 Interrupt-In Transfer...................................................................................... 881
22.6.1 Processing of Commands Transmitted by Control Transfer................................. 882
22.7 Stall Operations.................................................................................................................. 883
22.7.1 Overview .............................................................................................................. 883
22.7.2 Forcible Stall by Application ................................................................................ 883
22.7.3 Automatic Stall by USB Function Module ........................................................... 885
22.8 DTC Transfer..................................................................................................................... 886
22.8.1 Overview .............................................................................................................. 886
22.8.2 DTC Transfer for Endpoint 1................................................................................ 887
22.8.3 DTC Transfer for Endpoint 2................................................................................ 888
22.8.4 DTC Transfer End Interrupt ................................................................................. 889
22.9 Example of USB External Circuitry .................................................................................. 890
22.10 Usage Notes ....................................................................................................................... 892
22.10.1 Receiving Setup Data ........................................................................................... 892
22.10.2 Clearing the FIFO ................................................................................................. 892
22.10.3 Overreading and Overwriting the Data Registers ................................................. 892
22.10.4 Assigning Interrupt Sources to EP0...................................................................... 893
22.10.5 Clearing the FIFO When DTC Transfer is Enabled.............................................. 893
22.10.6 Notes on TR Interrupt ........................................................................................... 893
22.10.7 Restrictions on Peripheral Module Clock (φ) Operating Frequency..................... 894
Section 23 A/D Converter ................................................................................. 895
23.1 Features.............................................................................................................................. 895
23.2 Input/Output Pins............................................................................................................... 897
23.3 Register Descriptions......................................................................................................... 898
23.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 898
23.3.2 A/D Control/Status Register (ADCSR) ................................................................ 899
23.3.3 A/D Control Register (ADCR) ............................................................................. 901
23.4 Operation ........................................................................................................................... 902
23.4.1 Single Mode.......................................................................................................... 902
23.4.2 Scan Mode ............................................................................................................ 903
23.4.3 Input Sampling and A/D Conversion Time .......................................................... 905
23.4.4 Timing of External Trigger Input ......................................................................... 908
23.5 Interrupt Source ................................................................................................................. 909
23.6 A/D Conversion Accuracy Definitions .............................................................................. 909
Rev. 1.00 Mar. 12, 2008 Page xxiv of xIviii

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R4f2472R4f2462H8s/2462H8s/2400 seriesH8s/2472