22.5.4 Control Transfer.................................................................................................... 872
22.6.1 Processing of Commands Transmitted by Control Transfer................................. 882
22.7 Stall Operations.................................................................................................................. 883
22.7.1 Overview .............................................................................................................. 883
22.7.2 Forcible Stall by Application ................................................................................ 883
22.8 DTC Transfer..................................................................................................................... 886
22.8.1 Overview .............................................................................................................. 886
22.10 Usage Notes ....................................................................................................................... 892
22.10.1 Receiving Setup Data ........................................................................................... 892
22.10.2 Clearing the FIFO ................................................................................................. 892
22.10.3 Overreading and Overwriting the Data Registers ................................................. 892
22.10.5 Clearing the FIFO When DTC Transfer is Enabled.............................................. 893
22.10.6 Notes on TR Interrupt ........................................................................................... 893
22.10.7 Restrictions on Peripheral Module Clock (φ) Operating Frequency..................... 894
23.1 Features.............................................................................................................................. 895
23.2 Input/Output Pins............................................................................................................... 897
23.3 Register Descriptions......................................................................................................... 898
23.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 898
23.4 Operation ........................................................................................................................... 902
23.4.1 Single Mode.......................................................................................................... 902
23.4.2 Scan Mode ............................................................................................................ 903
23.5 Interrupt Source ................................................................................................................. 909
23.6 A/D Conversion Accuracy Definitions .............................................................................. 909
Rev. 1.00 Mar. 12, 2008 Page xxiv of xIviii