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2
Table 18.13
I
C Bus Timing (with Maximum Influence of t
Section 19 LPC Interface (LPC)
Table 19.1
Pin Configuration.................................................................................................. 668
Table 19.2
LADR1, LADR2 Initial Values ............................................................................ 684
Table 19.3
Host Register Selection......................................................................................... 685
Table 19.4
Slave Selection Internal Registers......................................................................... 685
Table 19.5
LPC I/O Cycle ...................................................................................................... 734
Table 19.6
GA20 Setting/Clearing Timing............................................................................. 740
Table 19.7
Fast Gate A20 Output Signals............................................................................... 742
Table 19.8
Scope of LPC Interface Pin Shutdown ................................................................. 744
Table 19.9
Scope of Initialization in Each LPC interface Mode............................................. 745
Table 19.10
Serialized Interrupt Transfer Cycle Frame Configuration ................................ 748
Table 19.11
Receive Complete Interrupts and Error Interrupt.............................................. 750
Table 19.12
HIRQ Setting and Clearing Conditions when LPC Channels are Used............ 752
Table 19.13
HIRQ Setting and Clearing Conditions when SCIF Channels are Used........... 753
Table 19.14
Host Address Example...................................................................................... 755
Section 20 Ethernet Controller (EtherC)
Table 20.1
Pin Configuration.................................................................................................. 759
Section 22 Ethernet Controller (EtherC)
Table 22.1
Pin Configuration.................................................................................................. 834
Table 22.2
Example of Limitations for Setting Values........................................................... 858
Table 22.3
Example of Setting................................................................................................ 859
Table 22.4
Relationship between TRNTREG0 Setting and Pin Output ................................. 861
Table 22.5
Relationship between Pin Input and TRNTREG1 Monitoring Value................... 862
Table 22.6
Interrupt Sources................................................................................................... 863
Table 22.7
Command Decoding on Application Side............................................................. 882
Table 22.8
Selection of Peripheral Module Clock (φ) when USB Connection is Made ......... 894
Section 23 A/D Converter
Table 23.1
Pin Configuration.................................................................................................. 897
Table 23.2
Analog Input Channels and Corresponding ADDR Registers .............................. 899
Table 23.3
A/D Conversion Characteristics (Single Mode).................................................... 907
Table 23.4
A/D Conversion Characteristics (Scan Mode) ...................................................... 907
Table 23.5
A/D Converter Interrupt Source............................................................................ 909
Table 23.6
Standard of Analog Pins ....................................................................................... 913
Section 25 Flash Memory
Table 25.1
Comparison of Programming Modes.................................................................... 920
Table 25.2
Pin Configuration.................................................................................................. 925
Table 25.3
Register/Parameter and Target Mode ................................................................... 927
/t
)........................................ 654
Sr
Sf
Rev. 1.00 Mar. 12, 2008 Page xlv of xIviii
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