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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.4
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit
Bit Name
7
TE
6
RE
5, 4
3
TEIE
2
TIE
1
RIE
0
CEIE
Rev. 1.00 Mar. 12, 2008 Page 558 of 1178
REJ09B0403-0100
Initial
Value
R/W
0
R/W
0
R/W
All 0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The initial value
should not be changed.
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, an RXI interrupt request and
an OEI interrupt request are enabled.
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
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