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Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Symbol
AS
IOS
CS256
RD
HWR
LWR
WAIT
WR
HBE
LBE
AH
AD15 to AD0
Rev. 1.00 Mar. 12, 2008 Page 108 of 1178
REJ09B0403-0100
I/O
Function
Output
Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-Kbyte
extended area is accessed (the CS256E bit in SYSCR is 1).
Output
Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
Output
Chip select signal indicating that the 256-Kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
Output
Strobe signal indicating that the external address space is
being read.
Output
Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is valid.
Output
Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is valid.
Input
Wait request signal when accessing the external space.
Output
Strobe signal indicating that the external address space is
being written to.
Output
Strobe signal indicating that the external address space is
being accessed, and the upper half (D15 to D8) of the data
bus is valid.
Output
Strobe signal indicating that the external address space is
being accessed, and the lower half (D7 to D0) of the data
bus is valid.
Output
Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
Input/Output
Address output and data input/output pins for address-data
multiplex extension.
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