Advertisement
Figure 23.9 Example of Analog Input Protection Circuit........................................................... 913
Figure 23.10 Analog Input Pin Equivalent Circuit ..................................................................... 914
Section 25 Flash Memory
Figure 25.1 Block Diagram of Flash Memory............................................................................ 918
Figure 25.2 Mode Transition of Flash Memory.......................................................................... 919
Figure 25.3 Flash Memory Configuration .................................................................................. 921
Figure 25.4 Block Division of User MAT.................................................................................. 922
Figure 25.5 Overview of User Procedure Program .................................................................... 923
Figure 25.6 System Configuration in Boot Mode....................................................................... 948
Figure 25.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 949
Figure 25.8 Overview of Boot Mode State Transition Diagram................................................. 951
Figure 25.9 System Configuration in USB Boot Mode .............................................................. 952
Figure 25.10 USB Boot Mode State Transition Diagram........................................................... 954
Figure 25.11 Programming/Erasing Overview Flow.................................................................. 956
Figure 25.12 RAM Map When Programming/Erasing is Executed ........................................... 957
Figure 25.13 Programming Procedure........................................................................................ 958
Figure 25.14 Erasing Procedure ................................................................................................. 963
Figure 25.15 Repeating Procedure of Erasing and Programming............................................... 965
Figure 25.16 Procedure for Programming User MAT in User Boot Mode ................................ 968
Figure 25.17 Procedure for Erasing User MAT in User Boot Mode .......................................... 970
Figure 25.18 Transitions to Error-Protection State..................................................................... 985
Figure 25.19 Switching between the User MAT and User Boot MAT ...................................... 986
Figure 25.20 Boot Program States.............................................................................................. 989
Figure 25.21 Bit-Rate-Adjustment Sequence ............................................................................. 990
Figure 25.22 Communication Protocol Format .......................................................................... 991
Figure 25.23 New Bit-Rate Selection Sequence....................................................................... 1002
Figure 25.24 Programming Sequence....................................................................................... 1006
Figure 25.25 Erasure Sequence ................................................................................................ 1009
Section 26 Boundary Scan (JTAG)
Figure 26.1 JTAG Block Diagram............................................................................................ 1020
Figure 26.2 TAP Controller State Transitions .......................................................................... 1043
Figure 26.3 Reset Signal Circuit Without Reset Signal Interference........................................ 1047
Figure 26.4 Serial Data Input/Output (1).................................................................................. 1048
Figure 26.5 Serial Data Input/Output (2).................................................................................. 1049
Section 27 Clock Pulse Generator
Figure 27.1 Block Diagram of Clock Pulse Generator ............................................................. 1051
Figure 27.2 Typical Connection to Crystal Resonator.............................................................. 1052
Figure 27.3 Equivalent Circuit of Crystal Resonator................................................................ 1052
Figure 27.4 Example of External Clock Input .......................................................................... 1053
Rev. 1.00 Mar. 12, 2008 Page xxxviii of xIviii
Advertisement
