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10.5.3
Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 10.10 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 10.11 shows the timing of this type of
conflict.
Figure 10.10 Conflict between OCR Write and Compare-Match
Write cycle of OCR
T 1
φ
Address
OCR address
Internal write
signal
FRC
OCR
Compare-match
signal
(When Automatic Addition Function is Not Used)
Section 10 16-Bit Free-Running Timer (FRT)
T 2
N
N + 1
N
M
Write data
Disabled
Rev. 1.00 Mar. 12, 2008 Page 387 of 1178
REJ09B0403-0100
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