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Type
Symbol
Interrupts
NMI
IRQ15 to
IRQ0
ExIRQ15 to
ExIRQ0
WAIT
Bus control
RD
HWR
LWR
AS/IOS
CS256
Pin No.
176-Pin
144-Pin
E2
11
N15,
79, 78,
M13, A6,
139, 138,
C6, B7,
136, 135,
D6, F2,
15, 16,
G4, C2,
4 to 2,
B1, C3,
140,
B6, B8,
132 to
A8, C8,
129
D8
N5, P5,
43 to 46,
R5, M6,
82 to 85,
M15, L13,
33 to 35,
L14, L15,
37 to 41
M3, N1,
M4, P1,
P2, N3,
P3, R3
17
G3
J2
25
C1
6
K4
26
G2
19
G3
17
I/O
Name and Function
Input
Nonmaskable interrupt request input pin
Input
These pins are used to request maskable
interrupts.
Either IRQn or ExIRQn can be selected
as the IRQn interrupt signal input pin.
Input
These pins are used to request maskable
interrupts.
Either IRQn or ExIRQn can be selected
as the IRQn interrupt signal input pin.
Input
Requests wait state insertion to bus
cycles when an external tri-state address
space is accessed.
Output Low level on this pin indicates that the
MCU is reading from an external address
space.
Output Low level on this pin indicates that the
MCU is writing to an external address
space.
The upper byte of the data bus is valid.
Output Low level on this pin indicates that the
MCU is writing to an external address
space.
The lower byte of the data bus is valid.
Output Low level on this pin indicates that the
address output on the address bus is
valid.
Output Indicates access to the 256-Kbyte area of
H'F80000 to H'FBFFFF.
Rev. 1.00 Mar. 12, 2008 Page 15 of 1178
Section 1 Overview
REJ09B0403-0100
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