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Section 19 LPC Interface (LPC)
Table 19.8 shows the scope of the LPC interface pin shutdown.
Table 19.8 Scope of LPC Interface Pin Shutdown
Abbreviation
Port
LAD3 to LAD0
PE3 to P30
LFRAME
PE4
LRESET
PE5
LCLK
PE6
SERIRQ
PE7
LSCI
PD0
LSMI
PD1
PME
PD2
GA20
PD3
CLKRUN
PD4
LPCPD
PD5
[Legend]
O:
Pin that is shutdown by the shutdown function
∆:
Pin that is shutdown only when the LPC function is selected by register setting
X:
Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by RES pin input, or WDT0 overflow)
All register bits, including bits LPC4E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
SDWNB bit is cleared to 0.
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 19.9.
Rev. 1.00 Mar. 12, 2008 Page 744 of 1178
REJ09B0403-0100
Scope of
Shutdown
I/O
O
I/O
O
Input
X
Input
O
Input
O
I/O
∆
I/O
∆
I/O
∆
I/O
∆
I/O
O
Input
X
Input
Notes
Hi-Z
Hi-Z
LPC hardware reset function is active
Hi-Z
Hi-Z
Hi-Z, only when LSCIE = 1
Hi-Z, only when LSMIE = 1
Hi-Z, only when PMEE = 1
Hi-Z, only when FGA20E = 1
Hi-Z
Needed to clear shutdown state
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