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15.3.6
Interrupt Enable Register (FIER)
FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR
is 0.
Bit
Bit Name
7 to 4
3
EDSSI
2
ELSI
1
ETBEI
0
ERBFI
Initial Value
R/W
All 0
R
0
R/W
0
R/W
0
R/W
0
R/W
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Reserved
These bits are always read as 0. The initial value
should not be changed.
Modem Status Interrupt Enable
0: Modem status interrupt disabled
1: Modem status interrupt enabled
Receive Line Status Interrupt Enable
0: Receive line status interrupt disabled
1: Receive line status interrupt enabled
FTHR Empty Interrupt Enable
0: FTHR empty interrupt disabled
1: FTHR empty interrupt enabled
Receive Data Ready Interrupt Enable
A character timeout interrupt is included when the
FIFO is enabled.
0: Receive data ready interrupt disabled
1: Receive data ready interrupt enabled
Rev. 1.00 Mar. 12, 2008 Page 511 of 1178
REJ09B0403-0100
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