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Section 19 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave
3
C/D3
0
2
DBU32
0
1
IBF3A
0
0
OBF3A
0
Note:
* Only 0 can be written to clear the flag.
Rev. 1.00 Mar. 12, 2008 Page 696 of 1178
REJ09B0403-0100
R/W
Host Description
R
R
Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
R/W
R
Defined by User
The user can use this bit as necessary.
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host writes to IDR3 in an I/O write cycle
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not transmit data in ODR3
[Clearing conditions]
•
When the host reads ODR3 in an I/O read cycle
•
When the slave writes 0 to bit OBF3A
1: There is transmit data in ODR3
[Setting condition]
•
When the slave writes to ODR3
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