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φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space
(2)
8-Bit, 3-State Data Access Space
Figure 6.18 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states can be inserted.
φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space
Read Cycle
Address
Data
T
T
T
1
2
3
Address
Read Cycle
Address
Data
T
T
T
T
T
1
AW
2
3
4
Address
Write Cycle
Address
T
T
T
4
1
2
Data
Address
Address
T
T
T
T
T
DSW
5
1
AW
2
Data
Address
Rev. 1.00 Mar. 12, 2008 Page 141 of 1178
Section 6 Bus Controller (BSC)
Data
T
T
3
4
Data
Write Cycle
Data
T
T
T
T
3
4
DSW
5
Data
REJ09B0403-0100
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