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18.4.2
Initialization
Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of
data.
Start initialization
Set MSTP4 = 0 (IIC_0)
MSTP3 = 0 (IIC_1)
MSTP2 = 0 (IIC_2, IIC_3)
MSTP0 = 0 (IIC_4, IIC_5)
(MSTPCRL)
Set IICE = 1 in STCR
Set ICE = 0 in ICCR
Set SAR and SARX
Set ICE = 1 in ICCR
Set ICSR
Set STCR and IICX3
Set ICMR
Set ICXR
Set ICCR
<< Start transmit/receive operation >>
Note: Be sure to modify the ICMR register after transmit/receive operation has been completed.
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to
BC0 will be modified erroneously, thus causing incorrect operation.
18.4.3
Master Transmit Operation
2
In I
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Cancel module stop mode
Enable the CPU accessing to the IIC control register and data register
Enable SAR and SARX to be accessed
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set acknowledge bit (ACKB)
Set transfer rate (IICX and TCSS)
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Figure 18.6 Sample Flowchart for IIC Initialization
2
Section 18 I
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 619 of 1178
REJ09B0403-0100
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