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Table 6.10 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Address Cycle)
AST256
WMS10
Table 6.11 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Data Cycle)
AST256
WMS1
0
—
1
1
0
6.4.2
Advanced Mode
The external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS
pin as an I/O strobe pin. The 256-Kbyte extended area (H'F80000 to H'FBFFFF) can be accessed
by the CS256 pin function.
The external address space is initialized as the basic bus interface and a 3-state access space. In
mode 2, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their
reserved areas is specified as the external address space. The on-chip RAM and its reserved area
are enabled when the RAME bit in SYSCR is set to 1, and disabled when the RAME bit is cleared
to 0. Addresses H'FF0800 to H'FFBFFF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F in
the on-chip RAM area and its reserved area are always specified as the external address space.
WC22
WC11
0
1
WC1
—
—
0
1
Section 6 Bus Controller (BSC)
Number of
Access
WC10
States
2
Number of
WC0
Access States
—
2
—
3
0
3
1
0
1
Rev. 1.00 Mar. 12, 2008 Page 123 of 1178
Number of
Program
Wait States
0
1
Number of
Program Wait
States
0
0
0
1
2
3
REJ09B0403-0100
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